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FULLY REMOTE- SR. Verification Engineer-System Verilog UVM If you are a FULLY REMOTE- SR. Verification Engineer-System Verilog UVM with experience, please read on!
What You Will Be Doing THESE POSITIONS ARE FOREVER FULLY REMOTE, I HAVE POSITIONS FROM MID LEVEL TO PRINICPAL LEVEL FOR THIS ROLE
Job Title: Design Verification Engineer of SOC
Skills in ASIC / FPGA verification (directed test or SystemVerilog / UVM)
Basic knowledge in design techniques Verilog or VHDL
Good knowledge of simulation flow
Good basis in scripting Python, Perl, Bash&
A good level in English, both writing and oral skills
You have to be rigorous and have a good analytical mind, you have to enjoy working in a team and being diplomatic, in particular when you have to point out the bugs discovered.
What You Need for this Position - VHDL/Verilog
- Verification Engineer
- FPGA Verification
What's In It for You - Vacation/PTO
So, if you are a FULLY REMOTE- SR. Verification Engineer-System Verilog UVM with experience, please apply today!
Colorado employees will receive paid sick leave. For additional information about available benefits, please contact Lizzy Faurot
- Applicants must be authorized to work in the U.S.
*CyberCoders, Inc is proud to be an Equal Opportunity Employer*
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, disability, protected veteran status, or any other characteristic protected by law.
*Your Right to Work* - In compliance with federal law, all persons hired will be required to verify identity and eligibility to work in the United States and to complete the required employment eligibility verification document form upon hire.
CyberCoders will consider for Employment in the City of Los Angeles qualified Applicants with Criminal Histories in a manner consistent with the requirements of the Los Angeles Fair Chance Initiative for Hiring (Ban the Box) Ordinance.